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Yijing Microelectronics
EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
2013 © Yijing Microelectronics All Rights Reserved
www.EGmicro.com
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Version change record
version number
date
description
V0.2
Internal test version of EG8030 data manual on January 25, 2013.
This version is for internal testing only!
Page 2
Yijing Microelectronics
EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
2013 © Yijing Microelectronics All Rights Reserved
www.EGmicro.com
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table of Contents 
1. Features............................................... ................................................. ................................................. .................. 4
2. Description............................................... ................................................. ................................................. .................. 4
3. Application field.............................. .................................................. ................................................. ........... 4
4. Pins............................................. ................................................. ................................................. ................... 4
4.1.
Pin definition............................................... ................................................. ............................ 4
4.2.
Pin description............................................... ................................................. ............................ 5
5. Structural block diagram.............................................. ................................................. ................................................. ........... 7
6. Typical application circuit............................................ ................................................. ................................................. .... 8
6.1
Three-phase synchronous closed-loop voltage stabilization mode——DC-AC-AC power frequency transformer Δ-Y boost structure (recommended).............. .... 8
6.2
Three-phase independent closed-loop voltage stabilization mode-high-voltage DC inverter three-leg four-wire output structure (test) ........................... ....... 9
7. Electrical characteristics.............................................. ................................................. ................................................. ......... 10
7.1
Limit parameters...................................... ................................................. .........................................10
7.2
Typical parameters...................................... ................................................. .........................................10
8. Working principle............................................ ................................................. ................................................. .......... 11
8.1
Three-phase synchronous open-loop voltage regulation... ................................................. .............................. 12
8.2
Three-phase synchronous closed-loop voltage stabilization............................ .................................................. ............................. 12
8.3
Three-phase independent open-loop voltage regulation... ................................................. .............................. 13
8.4
Three-phase independent closed-loop voltage stabilization............................ ................................................. ............................. 14
9. Application design.............................................. ................................................. ................................................. ......... 14
9.1
Voltage feedback sampling............................................ ................................................. .................................. 14
9.2
Output current feedback............................................... ................................................. .................................. 15
9.3
Temperature detection feedback......................................... ................................................. .................................. 15
9.4
PWM output type............................................ ................................................. ...................................16
9.5
Dead time setting.............................................. ................................................. ...................................17
9.6
Frequency setting............................................... ................................................. .......................................... 18
9.7
Soft start function.................................. ................................................. ................................19
Page 3
Yijing Microelectronics
EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
2013 © Yijing Microelectronics All Rights Reserved
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9.8
Phase sequence reversal function............................................ ................................................. .................................... 19
9.9
Phase clear function.............................................. ................................................. ...................................19
9.10
Sinusoidal analog signal output............................................. ................................................. ........................... 19
10.
RS232 serial communication interface............................................. ................................................. ...............................20
11.
Package size...................................... ................................................. ................................................. twenty two
Page 4
Yijing Microelectronics
EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
2013 © Yijing Microelectronics All Rights Reserved
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EG8030 chip data sheet
1. Features
∎ 5V single power supply
∎ External 16MHz crystal oscillator
∎ Four working modes of pin configuration
● Three-phase synchronous open loop voltage regulation
● Three-phase synchronous closed-loop voltage stabilization
● Three-phase independent open loop voltage regulation
● Three-phase independent closed-loop voltage stabilization
∎ Real-time processing of voltage, current, and temperature feedback
∎ Overvoltage, undervoltage, overcurrent, short circuit, overheating protection functions
∎ Pin 3S soft start
∎ Phase sequence reversal function
∎ Phase clear function
∎ One LED status indication and buzzer alarm
∎ One fundamental frequency output and one sinusoidal analog signal output
∎ One fan control output
∎ Pin setting 2 kinds of three-phase pure sine wave output frequency:
● 50Hz pure sine wave fixed frequency
● 60Hz pure sine wave fixed frequency
∎ PWM carrier frequency can be set
● 20KHz carrier frequency
● 10KHz carrier frequency
● 5 KHz carrier frequency
● 2.5KHz carrier frequency
∎ Built-in dead zone control, pins set 4 kinds of dead time:
● 300nS dead time
● 500nS dead time
● 1.0uS dead time
● 2.0uS dead time
∎ According to customer's application
Corresponding function or parameter
2. Description
EG8030 is a digital and fully functional three-phase pure sine wave inverter generator chip with dead zone control. It has four configurable
The operation mode can be applied to the DC-DC-AC two-stage power conversion architecture or the DC-AC single-stage power frequency transformer boost conversion architecture. External 16MHz crystal oscillator
It can generate a three-phase SPWM signal with high precision, low distortion and low harmonics. And it has a complete sampling mechanism that can collect current signals, temperature
Implementation of processing to achieve output voltage stabilization and various protection functions. The chip adopts CMOS technology and integrates SPWM inside
Sine generator, dead time control circuit, amplitude factor multiplier, soft start circuit.
3. Application areas
∎ Three-phase pure sine wave inverter
Page 5
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EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
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4. Pin
4.1. Pin definition
Figure 4-1. EG8030 pin definition
Description:
1. All configuration pins (DI) of the chip are weak pull-up input ports, and the internal pull-up resistance value is 30KΩ. When the pins are floating outside,
The pin is high level, that is, the configuration word read by the chip is "1"; if you need to configure it as "0", you can connect the pin directly to ground.
2. The chip feedback signal input pin (AI) is an analog signal input port, in high-impedance mode. When the pin is floating outside, it is an uncertain value.
The AD value read by ADC is uncertain.
3. All digital output pins (DO) of the chip are push-pull output ports, with a current source of 5mA and a sink current of 20mA.
4. The chip sine wave signal output (AO) pin is an analog signal output port, which is only used for small signals and has no current capability.
Page 6
Yijing Microelectronics
EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
2013 © Yijing Microelectronics All Rights Reserved
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4.2. Pin description
Pin No. Pin Name
Port mode
description
1
MOD0
DI
MOD1, MOD0 are to set the working mode of three-phase inverter,
"11" is the three-phase synchronous open-loop voltage regulation mode, that is, an analog signal is provided through the external VOLADJ pin
Control the modulation depth of the three-phase SPWM, 0-5V can be set to 0%-100% modulation depth;
"10" is the three-phase synchronous closed-loop voltage stabilization mode. The chip collects the three-phase output phase voltage and performs PI adjustment.
The modulation depth is automatically calculated. At this time, the three-phase output is synchronous output, that is, the three-phase SPWM modulation depth is the same;
"01" is the three-phase independent open-loop voltage regulation mode, that is, three sets of external simulations are sampled through AVFB\BVFB\CVFB
Signal, independently control the modulation depth of ABC three-phase;
"00" is a three-phase independent closed-loop voltage stabilization mode, and the output three-phase voltage is directly fed back to
AVFB\BVFB\CVFB pin, the chip performs PI adjustment, and independently calculates the modulation depth for the three phases ABC.
NOTE: modulation depth　 difference between the maximum amplitude and the minimum amplitude of this modulated wave the maximum amplitude of the carrier and most
The ratio of the sum of small amplitudes is expressed as a percentage. For the inverter, in the same DC bus input and negative
Under load conditions, the modulation depth of SPWM is basically proportional to the amplitude of the output sine wave.
2
MOD1
DI
3
NC
AI
Keep
4
NC
AI
Keep
5
I FB
AI
Load current feedback input terminal
6
T FB
AI
Temperature feedback input
7
BET
AI
Battery voltage monitoring port for over-voltage and under-voltage protection
8
FRQADJ
AI
Three-phase sine wave feedback voltage threshold, which can be used as a three-phase synchronous voltage regulation terminal
9
V FB A
AI
A phase sine wave output voltage feedback input terminal
10
V FB B
AI
B-phase sine wave output voltage feedback input terminal
11
V FB C
AI
C-phase sine wave output voltage feedback input terminal
12
PHDIR
DI
Phase sequence reversal control pin
"0" sets the current three-phase output phase sequence to ACB
"1" sets the current three-phase output phase sequence to ABC
13
PHCLR
DI
Phase sequence clear port, triggered by falling edge signal, adjust the phase of A phase sine wave to 0°
14
ENH
DI
Three-phase SPWM output enable pin
"0" turns off three-phase SPWM signal output
"1" turns on three-phase SPWM signal output
15
SST
DI
Soft start setting pin
"0" turn off soft start
"1" Each time the SPWM output is restarted, a soft start is performed for 3 seconds, during which the amplitude of the sine wave increases linearly.
16
CFG
DI
SPWM configuration selection pin
SPWM output frequency, modulation frequency, dead zone size, output level, working mode, soft start of EG8030
There are two configuration methods for dynamic and three-phase phase sequence. Usually, the external pin configuration is used when the chip is working alone.
Set FS\MFS\DT\TYP\MOD\SST\PHDIR pin to achieve; when using serial port communication, you can set
Set this pin to select the internal register configuration. For serial communication and internal register settings, see ****
"0" selects internal register configuration, used in serial communication
"1" selects external pin configuration, used when the chip works independently
Page 7
Yijing Microelectronics
EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
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Pin No. Pin Name
Port mode
description
17
XTAL1
16M crystal oscillator pin 1, need to connect a 22pF capacitor to ground
18
XTAL2
16M crystal oscillator pin 2, need to connect a 22pF capacitor to ground
19
VCC
VCC
+5V working power terminal of the chip
20, 21
NC
The pin is reserved by the system and must be left floating!
twenty two
led
DO
External LED alarm output, when a fault occurs, output low level "0" to light up the LED
Normal: Long light
Turn off: flash once, turn off for 2 seconds, keep looping
Overcurrent: flashes 2 times, off for 2 seconds, and keeps cycling; Undervoltage: flashes 4 times, off for 2 seconds, keeps cycling
Over-voltage: flashing 3 times, off for 2 seconds, keep cycling; Over-temperature: flashing 5 times, off for 2 seconds, keep cycling
twenty three
BEEP
DO
Buzzer alarm function:
Normal: No bid
Turn off: call once, stop for 2 seconds, and keep looping;
Overcurrent: call 2 times, stop for 2 seconds, and keep cycling; Over temperature: call 5 times, stop for 2 seconds, keep cycling;
Overvoltage: call 3 times, stop for 2 seconds, keep cycling; Undervoltage: call 4 times, stop 2 seconds, keep cycling;
twenty four
RXD
DI
Serial port communication function pin, baud rate 2400, data bit 8 bits, stop bit 1 bit, no parity
Usually when using serial communication, the CFG pin needs to be configured as "0"
25
TXD
DO
26
TYPH
DI
TYPH, TYPL are the output type selection of PWM upper and lower tube
"00" means that the output low level turns on the upper tube of the power tube, and the output low level turns on the lower tube of the power tube;
"01" means that the output low level turns on the upper tube of the power tube, and the output high level turns on the lower tube of the power tube;
"10" means the output high level turns on the upper tube of the power tube, and the output low level turns on the lower tube of the power tube;
"11" means that the output high level turns on the upper tube of the power tube, and the output high level turns on the lower tube of the power tube;
When designing the application, refer to the typical application circuit diagram, and configure the pin status reasonably according to the drive device.
Otherwise, the inconsistency will cause the upper and lower power MOS transistors to be turned on at the same time
27
TYPL
DI
28
MFS0
DI
MFS1, MFS0 is to set the output SPWM wave modulation frequency
"00" is the output 2.5KHz modulation frequency;
"01" is the output 5KHz modulation frequency;
"10" is the output 10KHz modulation frequency;
"11" is the output 20KHz modulation frequency;
29
MFS1
DI
30
DT0
DI
DT1, DT0 are to set the dead time of PWM output upper and lower MOS transistors:
"00" is 1.5uS dead time;
"01" is 1.0uS dead time;
"10" is 0.5uS dead time;
"11" is 0.3uS dead time
31
DT1
DI
32
FS1
DI
Output sine wave frequency setting pin
"00" reserved
"01" reserved
"10" set the output sine wave frequency to 60Hz
"11" set the output sine wave frequency to 50Hz
33
FS0
DI
34
SPWMCH
DO
SPWM output from the upper tube of the C-phase bridge arm
35
SPWMBH
DO
B-phase bridge arm upper tube SPWM output
36
SPWMAH
DO
A phase bridge arm upper tube SPWM output
Page 8
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EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
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Pin No. Pin Name
Port mode
description
37
SPWMCL
DO
SPWM output of C-phase bridge arm lower tube
37
SPWMCL
DO
SPWM output of C-phase bridge arm lower tube
38
SPWMBL
DO
B-phase bridge arm lower tube SPWM output
39
SPWMAL
DO
SPWM output of A-phase bridge arm lower tube
40
GND
GND
The end of the chip
41
ERO
DO
Fault signal output pin
Output "0" when the chip is in the protection output off state, output "1" for normal operation
42
SPO
DO
Voltage sampling output pin
Output a high level during voltage sampling, low level when not sampling
43
ASIN
AO
Sine wave analog signal output pin
Output a sine wave signal with the same frequency and phase as the A-phase SPWM wave, see 9.1 Voltage Feedback
44
FANCTR
DO
External fan control, when T FB pin detects that the temperature is higher than 45℃, output high level "1" to make the fan
Running, when the temperature drops below 40℃, output low level "0" to stop the fan
5. Structure diagram
Figure 5-1. EG8030 block diagram
Page 9
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EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
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6. Typical application circuit
6.1 Three-phase synchronous closed-loop voltage stabilization mode- DC-AC-AC power frequency transformer delta -Y boost structure (recommended)
V1
IRF840
V7
IRF840
R67
10mΩ
R38
4.7Ω
R43
10K
D14 IN4148
R53
4.7Ω
R56
10K
D21 IN4148
V2
IRF840
V8
IRF840
R39
4.7Ω
R44
10K
D15 IN4148
R54
4.7Ω
R57
10K
D22 IN4148
V3
IRF840
V9
IRF840
R40
4.7Ω
R45
10K
D16 IN4148
R55
4.7Ω
R58
10K
D23 IN4148
L
P7
L
P12
L
P19
C31
0.1uF
/100V
C32
0.1uF
/100V
C33
0.1uF
/100V
2
3
1
VIN
GND
+5V
U6L7805
C26
0.1uF
C25
10uF
/25V
C28
0.1uF
C27
10uF
/25V
C44
1000uF
/63V
C42
1000uF
/63V
C43
1000uF
/63V
+48V
R33
10K
RT1
NTC/10K
C29
0.1uF
Temperature Sensor
+5V
R34
10K
R29
10K
C30
0.1uF
+48V
R32
+5V
R30
2.2K
Q2
8050
F1
Cooling fan
T2
Trans Eq
D12
Bridge1
R31
10K
R35
10K
T3
Trans Eq
D13
Bridge1
R36
10K
R37
10K
T1
Trans Eq
D11
Bridge1
R27
10K
R28
10K
L
P5
L
P10
L
P17
L
P22
C41
0.47uF/400V
C39
0.47uF/400V
C40
0.47uF/400V
L
P6
L
P11
L
P18
L
P23
PH
DIR
PH
CLR
ENH
ASIN
ERO
BFO
AVFB
BV
FB
CV
FB
VADJ
TFB
IFBI
BET
FA
N
VSC
BH
O
VSB
AHO
VSA
CH
O
CLO
BLO
ALO
+5V
+15V
R66
10mΩ
R65
10mΩ
Constantan wire
VIN
1
VCC
2
CT
3
GND
4
ADJ
5
FB
6
OUT
7
IPK
8
U7
EG1181
C37
4.7uF
/25V
C38
470pF
C36
0.1uF
/100V
R41
200Ω
D20
SS18
L1
1mH
R42
51K
R49
4.7K
C34
100uF
/25V
C35
0.1uF
+15V
+15V
+15V
S1
SW-SPST
CVFB
BVFB
AVFB
L
P15
L
P21
Y1
16M
C2 22P
C4 22P
AVFB
BV
FB
CV
FB
VADJ
TFB
IFBI
BET
1
3
2
Q1S8050
R2
1K
LS1
Bell
D7
led
R1
1K
+5V
R3 10K
R4 10K
R5 10K
R6 10K
R7 10K
R8 10K
1
2
3
4
8
+ -
+ -
7
5
6
U5LM393
R11
20K
R13
1.5K
R10
10K
R12
10K C10
0.01uF
C11
0.01uF
R26
20K
R9
20K
C12
0.01uF
+5V
R16
100Ω
R18
100Ω
R19
100Ω
R20
100Ω
R21
100Ω
R15
1K
C18
0.1uF
C17
0.1uF
C19
1nF
C16
0.1uF
C15
0.1uF
C14
0.1uF
C13
0.1uF
R17
56K
R14
3K
C9
0.1uF
C8
10uF
/25V
C23
0.1uF
C24
10uF
/25V
R2510K
+5V
+15V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
twenty one
twenty two
twenty three
twenty four
25
26
27
28
29
30
P2
ASIN
ERO
BFO
FA
N
VSC
BH
O
VSB
AHO
VSA
R24
2Ω
D10
FR107
C22
10uF/25V
R23
2Ω
D9
FR107
C21
10uF/25V
R22
2Ω
D8
FR107
C20
10uF/25V
+15V
D6IN4148
D5IN4148
D4IN4148
D3IN4148
D2IN4148
D1IN4148
C70.1uF
C60.1uF
C50.1uF
VCC
HIN
LIN
GND
LO VS
HO
VB
EG3012
U2EG3012
VCC
HIN
LIN
GND
LO VS
HO
VB
EG3012
U3EG3012
VCC
HIN
LIN
GND
LO VS
HO
VB
EG3012
U4EG3012
1
2
3
4
5
6
P1
DEBUG
+5V
TDA
TCK
C1
0.1uF
C3
10uF
/25V
CH
O
CLO
BLO
ALO
PH
DIR
PH
CLR
ENH
JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8
JP11JP12
JP9
JP10
R68
10mΩ
MO
D0
MO
D1
SCP-
SCP+
IFB
TFB
BET
VADJ
AVFB
BV
FB
CV
FB
PHDIR
PHCLR
SD
SST
CFG
X1
X2
VDD
TDA
TCK
led
BEEP
RX
D
TXD
TY
PL
TYPH
DT0
DT1
MFS0
MFS1
FS0
FS1
CHO
BHO
AHO
CLO
BLO
ALO
GND
ERO
BFO
ASIN
FAN
(LQFP44)
EG8030
U1
EG8030
A
B
C
B
A
C
a
b
c
n
n
n
n
A
B
C
a
b
c
n
20V ( delta ) - 380V ( star )
EG8030+EG3012+EG1181 three-phase pure sine wave inverter typical application circuit diagram
This application uses a 48V battery as the DC bus power supply, uses EG8030 as the inverter main control unit, and drives the chip EG3012 through a half-bridge
Drive power MOSFET, three-phase full-bridge inverter output three-phase SPWM after three-phase power frequency transformer boost filter. Three-phase power frequency step-up transformer
With Δ-Y connection, the four-wire output phase voltage is 220V, and the line voltage is a pure sine wave three-phase power supply of 380V. +15V drive power required on board
The power source adopts DC-DC step-down switching power supply chip EG1181 for 48V step-down conversion. In this application, EG8030 works in three-phase synchronous closed-loop stable
Voltage mode, voltage feedback adopts three small transformers to isolate samples. Since synchronous voltage stabilization is adopted, the three-phase SPWM modulation depth is the same, so when
When the load is unbalanced, the three-phase voltage will have a certain offset. EG8030 has a voltage imbalance protection function, which will limit the maximum
The voltage will not exceed the preset 10%, and when the three-phase voltage is seriously unbalanced, the shutdown protection will be adopted. Synchronous closed-loop voltage regulation mode is EG8030
The recommended working mode of, has the advantages of easy implementation and high reliability.
Page 10
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EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
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6.2 Three-phase independent closed-loop voltage stabilization mode-high-voltage DC inverter three-leg four-wire output structure (test)
(Unavailable)
Figure 6-2. Typical application circuit diagram of EG8030+TLP250 three-phase pure sine wave inverter
Page 11
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EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
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7. Electrical characteristics
7.1 Limit parameters
No other instructions, under T A = 25℃
symbol
parameter name
Test Conditions
The smallest
maximum
unit
VCC
power supply
Vcc pin relative to GND
Voltage
-0.3
6.5
V
I/O
All input and output ports
All I/O pins to GND
Voltage
-0.3
5.5
V
Isink
Maximum output sink of output pin
Current
-
-
25
mA
Isource
Maximum output pull of output pin
Current
-
-
-5
mA
T A
Ambient temperature
-
-45
85
°C
Tstr
Storage temperature
-
-65
125
°C
Note: Exceeding the listed limit parameters may cause permanent damage inside the chip. Long-term operation under extreme conditions will affect the reliability of the chip.
7.2 Typical parameters
Without other instructions, at T A = 25℃, Vcc=5V, OSC=12MHz
symbol
parameter name
Test Conditions
The smallest
typical
maximum
unit
Vcc
power supply
-
3.5
5
5.5
V
VREF
Reference power input
-
-
5
-
V
I/O
All input and output
Voltage of all I/O pins to GND
0
-
5
V
Icc
Quiescent Current
Vcc=5V, OSC=12MHz
-
10
15
mA
V FB
Peak feedback reference voltage
Vcc=5V
-
3.0
-
V
I FB
Current protection reference voltage
Vcc=5V
-
0.5
-
V
T FB
Temperature protection reference voltage
Vcc=5V
-
4.3
-
V
Vin(H)
Input logic signal high potential
Vcc=5V
2.0
5.0
5.5
V
Vin(L)
Input logic signal low level
Vcc=5V
-0.3
0
1.0
V
Vout(H)
Output logic signal high level
Vcc=5V,IOH=-3mA
3.0
5.0
-
V
Vout(L)
Output logic signal low level
Vcc=5V, IOL=10mA
-
-
0.45
V
Isink
Maximum output sink of output pin
Current
-
-
-
20
mA
Isource
Maximum output pull of output pin
Current
-
-
-
-3
mA
Page 12
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EG8030 chip data manual V0.2
Three-phase SPWM inverter dedicated chip
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8. Working principle
EG8030 has four working modes: three-phase synchronous open-loop voltage regulation, three-phase synchronous closed-loop voltage regulation, three-phase independent open-loop voltage regulation, and three-phase
Independent closed-loop voltage regulation. The four working modes have their own characteristics and can be independently selected by users according to their needs. Before introducing the four working modes, first introduce
Let's look at an important parameter of EG8030 voltage control system-modulation depth.
The modulation depth is defined as: the ratio of the difference between the maximum amplitude and minimum amplitude of the current modulated wave to the sum of the maximum amplitude and minimum amplitude of the carrier,
Expressed as a percentage. For the inverter, under the same DC bus input and load conditions, the modulation depth of SPWM is comparable to that of the output sine wave.
The amplitude is basically proportional.
The relationship between DC bus voltage, modulation depth, and output sine wave
The figure below shows the relationship between the DC bus voltage, modulation depth and output sine wave. VDC in the figure represents the DC bus
Voltage, m represents the modulation depth. In an ideal state, that is, when the output impedance of the inverter is 0, when the modulation depth m=100%, the peak of the sine wave
The peak value is exactly equal to the DC bus voltage. From this we can get the relationship between the single-phase sine wave voltage and the DC bus voltage as:
VAC TOP =
2
1
* m * VDC
VAC RMS =
4
2
* m * VDC
E.g:
1) DC bus voltage VDC = 650V, modulation depth m = 100%, the effective value of the current AC output voltage can be calculated:
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VAC RMS =
4
2
* 650 * 100% = 230V
2) DC bus voltage VDC = 650V, modulation depth m = 50%, the effective value of the current AC output voltage can be calculated:
VAC RMS =
4
2
* 650 * 50% = 115V
In EG8030, we define the modulation depth of the three-phase SPWM M A , M B , M C .
8.1 Three-phase synchronous open loop voltage regulation
The three-phase synchronous open-loop voltage regulation mode is the simplest working mode of EG8030. The chip works in open loop mode, and the user adjusts
VOLADJ voltage three-phase direct control pin SPWM modulation depth M A , M B , M C , and the three-phase modulation depth M A = M B = M C . VOLADJ
0-5V feet corresponding to the voltage modulation depth M A 0-100% of. In order to ensure that the waveform is a complete sine wave in one cycle, the modulation of each phase
Made of only refreshed once a week depth, i.e. to VOLADJ sampling A-phase when the phase is 0 °, and in terms of M A , M B , M C values.
Three-phase synchronous open-loop voltage regulation can be applied to occasions where the accuracy of the three-phase AC output voltage is not high. Just provide a relatively stable high
Voltage DC power supply and a three-phase output filter can adjust the voltage on the VOLADJ pin to make the output voltage reach the target value. Simple structure, content
Easy to implement. The disadvantage is that since the actual inverter power supply is not an ideal voltage source, there will always be a certain output impedance. When the load increases,
The internal resistance of the inverter will lose part of the voltage, resulting in a decrease in the actual output voltage. The magnitude of the voltage drop is related to the internal resistance of the inverter. In addition,
The fluctuation of the DC power supply will also affect the three-phase output voltage.
Three-phase synchronous open-loop voltage regulation can also be applied to the occasions where the user builds the feedback loop, and the user can participate in the realization through the hardware circuit or the single-chip software
Various control algorithms perform closed-loop voltage stabilization. At this time, EG8030 acts as an actuator, adjusting the sine wave according to the voltage input on the VOLADJ pin
Output. This way of working opens up the application of the chip more and provides developers with ample space for independent play. But it should be noted that
The output adjustment mechanism of EG8030 is weekly adjustment, that is, the output is changed once per cycle. In one cycle, the voltage change on the VOLADJ pin will change
Will not be responded.
8.2 Three-phase synchronous closed-loop voltage stabilization
The three-phase synchronous closed-loop voltage stabilization mode is the recommended application mode of the EG8030, which is suitable for occasions that require precision of the output voltage. Working in this
In the mode, the chip samples the feedback signals on the AVFB, BVFB, and CVFB pins and takes the average value to obtain the current three-phase average feedback voltage.
The three-phase SPWM modulation depth M A , M B , M C are obtained through the internal PI regulator operation , and M A =M B =M C , and the three-phase output is adjusted synchronously.
VOLADJ determines the threshold of feedback control. For example, the current voltage on the VOLADJ pin is 2.5V, then when the average feedback voltage is greater than 2.5V,
EG8030 gradually reduces the values ​​of M A , M B , and M C through the internal PI regulator calculation , thereby reducing the output voltage, and the feedback voltage will also follow
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On the other hand, when the A-phase feedback voltage is less than 2.5V, the EG8030 will synchronously reduce M A , M B , M C through the calculation of the internal PI regulator
The value of, thereby reducing the output voltage, and at the same time the feedback voltage will also decrease; in this way, the voltage feedback can be stabilized at 2.5V, and the output voltage
Naturally it will remain constant.
In this mode, when the DC bus voltage fluctuates or the load changes, the three-phase output voltage can basically remain constant. Suitable for pair loss
When the output voltage accuracy is high and the load balance or the load difference is not big. When any phase voltage is greater than 110% of the set voltage or less than the set voltage
When the voltage is 90%, EG8030 will perform the three-phase unbalance protection shutdown operation.
Three-phase synchronous closed-loop voltage stabilization requires sampling of high-voltage output for feedback, so it is generally recommended that users use three-phase power frequency transformers to boost the voltage and output
The phase voltage needs to use three small feedback transformers for isolation and step-down feedback. Ensure the isolation between DC output and AC output, and the control circuit is
AC output isolation. It is recommended to use Δ-Y connection for three-phase power frequency step-up transformers, which can obtain four-wire output and increase the DC voltage
Utilization rate. The high-voltage end of the three-phase power frequency transformer needs to connect a small CBB filter capacitor to the center line to obtain a smooth three-phase sine wave.
8.3 Three-phase independent open loop voltage regulation
Three-phase independent open-loop voltage regulation mode is another open-loop operating mode of EG8030. The user adjusts the AVFB, BVFB, CVFB pins
The voltage on the three-phase SPWM independently controls the modulation depth M A , M B , and M C of the three-phase SPWM . The corresponding relationship is 0-5V corresponds to 0-100%, where AVFB control
Manufactured by M A , the control BVFB M B , the control CVFB M C . In this mode, the VOLADJ pin function is shielded. In order to ensure that within one cycle
The waveform is a complete sine wave, and the modulation depth of each phase is only refreshed once per cycle, that is, when the phase of each phase is 0°, the feedback is collected.
Like this, and convert the values ​​of M A , M B , and M C.
The three-phase independent open-loop voltage regulation can be applied to the occasions where the accuracy of the three-phase AC output voltage is not high, but the three-phase different voltage values ​​need to be output.
Only need to provide a relatively stable high-voltage DC power supply and a three-phase output filter, you can independently adjust AVFB, BVFB, CVFB
The voltage on the pin makes the output voltage of each phase reach different target values. The structure is simple and easy to implement. The disadvantage is that the actual inverter power supply is not
It is an ideal voltage source, and there will always be a certain output impedance. When the load increases, the internal resistance of the inverter will lose part of the voltage, resulting in actual
The actual output voltage has decreased. The magnitude of the voltage drop is related to the internal resistance of the inverter. In addition, the fluctuation of the DC power supply will also affect the three-phase output voltage.
Three-phase independent open-loop voltage regulation can also be applied to the occasions where users build their own feedback loops, and users can participate in the implementation through hardware circuits or single-chip software
Various control algorithms perform closed-loop voltage stabilization. At this time, EG8030 acts as an actuator, adjusting the sine wave according to the voltage input on the VOLADJ pin
Output. This working mode opens up the application of the chip more on the basis of the synchronous open-loop voltage regulation mode, and provides developers with a wide range of freedom.
Main play space. But it should be noted that the output adjustment mechanism of EG8030 is weekly adjustment, that is, the output is changed once per cycle.
Here, the voltage changes on the AVFB, BVFB, and CVFB pins will not be responded to
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8.4 Three-phase independent closed-loop voltage stabilization
The three-phase independent closed-loop voltage stabilization mode is a test mode of EG8030, which is suitable for the field with high accuracy of output voltage and three-phase unbalanced load.
Together. This mode has high DC voltage, complex structure, and is not as reliable as other modes, so it is defined as a test mode. Users need to be careful
Choose this working mode carefully.
In this working mode, the chip samples the feedback signals on the AVFB, BVFB, and CVFB pins, and performs calculations by independent PI regulators for each phase.
Obtain the modulation depth M A , M B , M C. of each box . VOLADJ still determines the threshold of feedback control, such as the current voltage on the VOLADJ pin
Is 2.5V, then the A-phase when the feedback voltage is greater than 2.5V, EG8030 reduced by the internal operation of the PI regulator M A value, thereby reducing the output
Output voltage, and the feedback voltage will decrease accordingly; conversely, when the phase A feedback voltage is less than 2.5V, the EG8030 will pass the internal PI regulator
Reducing operational M A value, thereby reducing the output voltage, the feedback voltage also decreases at the same time; thus, it is possible to stabilize the voltage feedback at 2.5V,
The output voltage will naturally remain constant. The other two phases also realize independent voltage regulation in the same way.
In this mode, when the DC bus voltage fluctuates or the load changes, the three-phase output voltage can basically remain constant. Suitable for pair loss
High precision output voltage, with three-phase unbalanced load occasions. This mode requires the use of two large capacitors in series to form the fourth bridge arm to achieve three-phase
Four-wire output and independent voltage regulation for each phase. Further technical support for this model will be gradually improved.
9. Application design
9.1 Voltage feedback
The voltage feedback sampling of the EG8030 chip adopts weekly sampling, the phase of the sampling point is determined by the current working mode, and the three-phase independent feedback working mode
Under the formula, the sampling point of each phase is the peak position of the sine wave of each phase, that is, the voltage feedback sampling is performed when the phase of each phase is 90°. Sampling in three-phase synchronous working mode
The point phase is 60°. The signal output by the SPO pin of the chip is a sampling signal, that is, the chip performs voltage feedback sampling during the high level of SPO.
In order to distinguish the sampling points of the three-phase feedback of A, B, and C, the wide level in the figure is the A-phase voltage feedback sampling point, followed by the B-phase sampling point and C
Phase sampling point. If the phase inversion is set (PHDIR='0'), the C-phase sampling point and the B-phase sampling point are followed by the wide level.
SPO and VFBA waveforms
SPO and VFBB waveforms
SPO and VFBC waves
A phase sampling point
B phase sampling point
C-phase sampling point
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The above waveform is taken from the feedback waveform when the power frequency transformer Δ-Y connection is used in the three-phase synchronous closed-loop voltage stabilization mode. See 6.1 for circuit schematic
Section, the typical application schematic diagram of three-phase synchronous closed-loop voltage stabilization. The phase of the AVFB sampling point is 30°. Due to the Δ-Y connection of the power frequency transformer,
The input stage AC corresponds to the output stage with the same name terminal an, BA corresponds to the same name terminal bn, and CB corresponds to the same name terminal cn. Phase A is 0°, Phase C is -120°,
Then the phase of the line voltage AC is -60°, and the phase of the output stage an is also -60°. Therefore, the peak value of an is just sampled at the position of 30°.
The waveforms of BVFB and CVFB move backward by 120°. If the phase inversion (PHDIR='0') is set, then the BVFB, CVFB
The sampling point positions will be exchanged.
A
B
C
B
A
C
a
b
c
n
n
n
n
A
B
C
a
b
c
n
Three-phase power frequency transformer Δ-Y type connection
9.2 Current feedback
The pin I FB of the EG8030 chip is to measure the inverter output load current, which is mainly used for over-current protection detection. The circuit structure is shown in Figure 8.1a. Current
In the sampling feedback part, the reference peak voltage inside this pin is set to 0.5V. The overcurrent detection delay time is 600mS. When some reason causes the load to be
If the current is higher than the load current of the inverter, EG8030 will output xHO, xLO to "0" or according to the setting status of pins TYPH and TYPL.
"1" level, turn off all power MOSFETs to make the output voltage to low level. This function is mainly to protect the power MOSFETs and the load. Once
After entering the over-current protection, EG8030 will release and turn on the power MOSFET after 16S, then judge the load over-current situation, and release and turn on the power
The duration of the MOS tube is 100mS, and the overcurrent event will be judged within the released 100mS time. If there is still an overcurrent event, the EG8030 will
Turn off all power MOSFETs to bring the output voltage to low level, and wait for the release of 16S again. If the starting current is relatively large for some occasions
If it is relatively long and is not suitable for applying this function, you can ground the I FB pin.
9.3 Temperature feedback
The pin T FB of the EG8030 chip is used to measure the working temperature of the inverter, mainly used for over-temperature protection detection and control of the fan output, circuit structure
Figure 8.3a temperature detection circuit, as shown in the figure, the NTC thermistor R T 1 and the measuring resistor R F 1 form a simple voltage divider circuit.
The value changes as the temperature changes, and the size of this voltage will reflect the size of the NTC resistance to get the corresponding temperature value. Use 25℃ for NTC
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Corresponding to a thermistor with a resistance of 10K, the over-temperature voltage of the T FB pin is set at 4.3V. When over-temperature protection occurs, the EG8030 is based on pins TYPH,
The setting state of TYPL will output PWMXH, PWMXL to "0" or "1" level, turn off all power MOSFETs to make the output voltage reach
Low level, once the over-temperature protection is entered, the EG8030 will re-judge the operating temperature. If the voltage of the T FB pin is lower than 4.0V, the EG8030 will
Exit the over-temperature protection, and the inverter works normally. If the over-temperature protection function is not used, this pin needs to be grounded.
Figure 8.4a EG8030 temperature detection circuit
9.4 PWM output type
The pins TYPH and TYPL of the EG8030 chip can independently set the output type of the PWM upper and lower tubes to be suitable for various drives. TYPH, TYPL
When it is "00", the output PWM type output is applied to the occasions where the dead zone level is at the same time low level (such as driving IR2110 or IR2106 drive core
Figure 8.4a is the output waveform of EG8010 pin SPWMOUT, which effectively drives the power MOS tube at high level. Figure 8.4b is TYPH,
The application circuit for driving IR2110 when TYPL is "11".
+15V
+400V
+15V
+5V
EG8030
PWMXH
PWMXL
SPWM generator
State controller
TYPL="0" 26
IR2110
LO
COM
VCC
NC
NC
VS
VB
HO
NC
NC
NC
VDD
HIN
SD
LIN
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TYPH="0" 27
Figure 8.4a PWM waveform output when THPH=1 and TYPL=1
Figure 8.4b EG8030 drives IR2110
When TYPH and TYPL are "10", the output PWM type output is applied to the drive that the upper tube is turned on at high level and the lower tube is turned on at low level.
Driving circuit (such as driving IR2103 and other driving chips), Figure 8.4c is the output waveform of EG8030 pins xHO and xLO.
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+400V
+15V
EG8030
PWMXH
PWMXL
SPWM generator
State controller
TYPL="0" 26
LO
COM
VS
VB
HO
HIN
LIN
VSS
1
2
3
4
5
6
7
8
TYPH="0" 27
Figure 8.4c PWM waveform output when THPH=0, TYPL=1
Figure 8.4d EG8030 drives IR2103
When TYPH and TYPL are "01", the output PWM type output is applied to the driver whose upper tube is turned on at low level and the lower tube is turned on at high level.
Driving circuit (this kind of driving method is not commonly used), Figure 8.4e is the output waveform of EG8030 pins xHO and xLO.
Figure 8.4e PWM waveform output when THPH=1, TYPL=0
When TYPH and TYPL are "11", the output PWM type output is applied to the drive circuit whose upper tube and lower tube are both turned on at low level (such as
Drive the cathode of TLP250 and other optocoupler devices), Figure 8.4f is the output waveform of EG8030 pins xHO and xLO. , Low-level effective drive optocoupler,
The optocoupler output high-level drive power MOS tube, Figure 8.4g is when TYPH, TYPL is "11", EG8030 drives TL250 optocoupler device
Application circuit.
Figure 8.4f PWM waveform output when THPH=0, TYPL=0
Figure 8.4g EG8030 drives TLP250
9.5 Dead time
The pins DT1 and DT0 of the EG8010 chip control the dead time. The dead time control is one of the important parameters of the power MOS tube.
If the zone time is too small, the upper and lower power MOSFETs will be turned on at the same time and burn the MOSFET. If the dead zone is too large, it will cause waveform distortion and power transistors.
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Serious thermal phenomenon. Figure 8.5a shows the internal dead-time control sequence of EG8010. As shown in the figure, pins DT1 and DT0 are used to set 4 kinds of dead-time.
300nS dead time, "01" is 500nS dead time, "10" is 1uS dead time, "11" is 1.5us dead time.
300nS
XH0
XLO
300nS
DT1,DT0=11
500nS
500nS
DT1,DT0=10
1uS
1uS
DT1,DT0=01
2uS
2uS
DT1,DT0=00
XH0
XLO
XH0
XLO
XH0
XLO
Figure 8.5a EG8010 dead zone control setting
9.6 Frequency setting
EG8030 can be configured with two output sine wave frequencies, which are set by the FS0 pin. When the FS0 pin is floating or connected to high level, EG8030
A 50HZ sine wave will be generated. When the FS0 pin is connected to a low level, the EG8030 will generate a 60HZ sine wave.
In addition, EG8030 can also configure four SPWM modulation frequencies, which are set by pins MS1 and MS0.
MS1, MS0 = 11: Modulation frequency 20KHz
MS1, MS0 =10: modulation frequency 10KHz
MS1, MS0 = 01: modulation frequency 5KHz
MS1, MS0 =00: modulation frequency 2.5KHz
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9.7 Soft start
EG8030 provides a soft-start mode, which is suitable for loads with large instantaneous current. When the SST pin is configured as "1" through a pull-up resistor,
Enable this function. The soft start lasts for 3S, after 3S, it will automatically enter the voltage stabilization state. When set to "0", the soft start function is prohibited. EG8030 recommended
Enable the soft start function. If the soft-start function is enabled, when the chip restarts after the EN pin or the protection function is turned off, the chip will still soft-start.
start up.
9.8
Phase sequence reversal
EG8030 has a phase sequence reversal function, which can adjust the phase sequence direction. This function is realized through the PHDIR pin. When PHDIR is "1" B
The phase leads the A phase by 120°, the C phase lags the A phase by 120°, when it is "0", the B phase lags the A phase by 120°, and the C leads the front and back A phase by 120°. Phase sequence reversal
It can be used for motor control, but in order to prevent the motor from suddenly switching to reverse rotation and causing a large current impact, the output should be turned off first, and the motor should be stopped.
After down, the phase sequence is reversed, and then the output is enabled.
9.9
Phase clear
EG8030 has a phase clearing function and can synchronize the phase sequence online. Up-modulation on the PHCLR pin will trigger this function. After clearing A
The phase sequence is forced to clear, and the phases B and C will be adjusted to lead and lag 120° according to the direction status on the PHDIR. The user wants to
When the chip EG8030 is used synchronously, the FOUT pin of one chip can be connected to the PHDIR pin of the other chip to realize the phase synchronization of the two chips.
9.10 Sinusoidal analog signal output
EG8030 integrates DA module, which can output sine wave analog signal with the same phase as A.
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10. RS232 serial communication interface
EG8030 is applied to the RS232 serial communication interface to set the inverter's voltage, frequency, dead zone and other parameters. The application requires optical coupling isolation communication
As shown in Figure 8.9a.
VCC
GND
16
15
Figure 8.9a RS232 optocoupler isolation communication circuit
Serial port parameters:
Baud rate: 2400
Data bits: 8
Check Digit: None
Stop bit: 1
Protocol description:
In communication, EG8010 is used as a slave, and users can use MCU or PC as the master. Once the slave receives the command sent by the master, it will immediately
Generate a response and reply data to the host.
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The data format is shown in the figure. In one operation, the host sends two bytes of data, the first byte is the command byte, and the second byte is the data
byte. After receiving two bytes from the master, the slave returns four bytes of data immediately.
Command format: (reserved)
CODE DATA
BYTE1
BYTE4
BYTE2 BYTE3
Host sends:
Return from the machine:
Communication protocol data format
Serial port parameters: 2400 8 N 1
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11. Package size
LQFP44 package size:
Symbol A A1 A2 A3
b
b1
c
c1
D D1
E E1
e eB L L1
θ
MIN-0.05 1.35 0.59 0.29 0.28 0.13 0.12 11.80 9.90 11.80 9.90
0.80
BSC
11.25 0.45
1.00
BSC
0
NOM-
-1.40 0.64-0.30-0.13 12.00 10.00 12.00 10.00
-
-
-
MAX 1.60 0.20 1.45 0.69 0.37 0.33 0.18 0.14 12.2010.1012.2010.10
11.45 0.75
7
Unit mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm
O

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