// MOD: added the following 2 lines
EICRA = _BV(ISC01) | _BV(ISC00);
EIMSK = _BV(INT0);

ISR(INT0_vect)
{
if (pcount < 50) // Arbitrary window.
{ TCNT2=126; // Reset as if
pcount=0; // Timer 2 overflow
TCNT1=0; // happens
}
}

ISR(TIMER1_OVF_vect)
{
//20Khz SPWM
long c;
if(pcount == 1) // order of events is important. This gives the least time difference from 50Hz and 20kHz gate drive
{ // When this difference is big, larger AC output waveform distortion occurs.
if (f50 == 1)
cbi(PORTD,7); <<<< raise PD7
else
sbi(PORTD,7); <<<< lower PD7
}
c = (l[pcount] * vpwr) >> 14; // scale sin wave by vpwr 32 bit integer calcs.
if (f50 == 1) // one 1/2 wave or other of 50Hz output
OCR1A = c;
else
OCR1A = PPWM - c;
pcount++;
}

TCCR1A = _BV(COM1A1) | _BV(COM1B0) | _BV(COM1B1) | _BV(WGM11);

sbi(DDRB,1);

for(t=0.0,i=0; i <= NPWM; i++,t += 2.0 * 3.14159/ (float) NPWM)
{
u = 8192.0 * sin(t);
l = 8192 + (int)u;
}
..
pinMode(9, OUTPUT);
pinMode(10, OUTPUT); // enable OCRB1 output pin

..
ISR(TIMER2_OVF_vect)
{ // 100Hz enable switch check, sets flag to run PID loop, ramp up etc.
TCNT2=100;
uf=1;
if(oen == 1)
sbi(PORTD,5);
else
cbi(PORTD,5);
check_switch();
}

..
ISR(TIMER1_OVF_vect)
{//20Khz SPWM
long c,d;
uint16_t p2;

c = (l[pcount] * vpwr) >> 14; // scale sin wave by vpwr 32 bit integer calcs.
OCR1A = c;

p2 = pcount + NPWM/2; // shift wave form table index 50% forward
if (p2 >= NPWM) // wrap around the index if needed
p2 -= NPWM;
d = (l[p2] * vpwr) >> 14; // scale sin wave by vpwr 32 bit integer calcs.
OCR1B = PPWM - d; // OCRB is compliment so we need to compliment it again!

pcount++; // free running PWM now, no longer reset by timer2 OVF
if(pcount >= NPWM)
{
pcount = 0;
sbi(PORTD,7); // give a sync pulse for DSO, aligned with start of 50Hz
cbi(PORTD,7);
}
}