cbi (DDRD,2);sbi (PORTD,2); // setup INTO port for zero crossing sync
sbi (DDRD,3);sbi (PORTD,3); // setup INT1 port for software interrupt

// INT0: rising edge input, INT1: low level (needs DDRD3 configured as output for software generated interrupt)
EICRA |= _BV(ISC01) | _BV(ISC00);
EIMSK |= (1<<INT1) | (1<<INT0);

ISR(INT0_vect) // for optional external sync
{
if (pcount < 10) // arbitrary window
{
if (FundHz == 60)
{TCNT0=FundFx2 + Fudge60Hz;} // add fudge factor
else
{TCNT0=FundFx2;}
pcount = 0; TCNT1 = 0; // reset
}
}

ISR(INT1_vect) // triggered by code in TIMER1_OVF_vect
{
sbi (PORTD,3); // prevent multiple interrupts, turn off trigger
c = (l[pcount] *vpwr ) >> 14; // vpwr scale sin wave by vpwr 32 bit integer calcs.
c2 = c + 1; // dead time for 2LO trailing edge.
if (c2 > PPWM){c2 = PPWM;} // just in case.
OCR1A = c; OCR1B = c2; // update
pcount++;
}

#include "C_ASM_Reg.h"

; Adjust the following Port Pin assignment to match your schematic. Assigned pins must have pull-down resistors (1k to 4.7k)
; Nano D5 (PD5) = SPWMOUT1 (1HI) LF (unipolar paired with SPWMOUT4)
; Nano D6 (PD6) = SPWMOUT2 (1LO) LF (unipolar paired with SPWMOUT3) (shorter hi level duration for dead time)
; Nano D9 (PB1) = SPWMOUT3 (2HI) HF (fixed to OC1A pin) (unipolar paired with SPWMOUT2)
; Nano D10 (PB2) = SPWMOUT4 (2LO) HF (fixed to OC1B pin) (unipolar paired with SPWMOUT1)
;--------------------------------------------------------
.global TIMER1_OVF_vect
TIMER1_OVF_vect:
nop
nop
sbi _SFR_IO_ADDR(DDRB),PB1 // sequence adds 2 cycles
; sbi _SFR_IO_ADDR(DDRB),PB2 // dead time for 2LO
in sreg_save, _SFR_IO_ADDR(SREG)
tst FundFF ; flip-flops at fundamental*2 rate
breq OVF2
; FundFF ne 0, lower PD6, raise PD5
cbi _SFR_IO_ADDR(PORTD),PD6 ; 2 cycles, Fundamental
;; rcall DTDLYO ; 3 cycles. If commented, dead time is system clock(62.5 nSec.) x 2
sbi _SFR_IO_ADDR(PORTD),PD5 ; 2 cycles, Fundamental
jmp FundFFdone
OVF2:
; FundFF eq 0, lower PD5, raise PD6
cbi _SFR_IO_ADDR(PORTD),PD5 ; 2 cycles, fundamental
;; rcall DTDLYO ; 3 cycles. If commented, dead time is system clock(62.5 nSec.) x 2
sbi _SFR_IO_ADDR(PORTD),PD6 ; 2 cycles, fundamental
FundFFdone:
clr FundZeroX
cbi _SFR_IO_ADDR(PORTD),PD3 ; signal mainline's INT1 handler
out _SFR_IO_ADDR(SREG), sreg_save
reti ; done
;---------------------------------------------------------