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LadyN

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Posted: 06:35pm 11 Mar 2019

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The Warpverter brain takes in DC power, say from batteries, rectified AC, PV Panels and the like and generates control signals for H-Bridges that drive transformer stages.

The Warpverter has a very unique design - it's actually composed of cascading inverters (hence StepInverter) that assemble harmonics of square waves to create a practically pure sine wave output.

The THD of the Warpverter decreases as we increase the number of cascades with each cascade handling less power than the previous in proportion to their harmonic coefficient.

Tony has implemented the brains using discrete digital gates, an ADC and an EEPROM.

The EEPROM data generation itself requires a separate thread because it's not very intuitive.

In this thread, we assume the EEPROM is available and programmed.

Here is a schematic of the Warpverter brain control board.

https://imgur.com/a/aAcK4A1

Attached is the BOM from the schematic. 2019-03-12_043439_BOM_for_Step_Inverter_rev_1.0.zip

Below is an detailed post from Tony to explain how it works:

LadyN

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Posted: 06:38pm 11 Mar 2019

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LadyN

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Posted: 06:42pm 11 Mar 2019

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Warpspeed said Crystal oscillator module U5 drives U10 and U6 both of which are just straight multi stage binary ripple counters, each successive stage dividing the frequency by two. These address the ten lower bits of the EEPROM so that the addresses just cycle through from 000 to 3FF endlessly. That would be just one of the 1K lookup table that contains the data bits for one complete sinusoidal cycle that repeats at 50Hz.

Every time the address bits change, there is a moment of noise and total chaos until the EEPROM output data is completely stable. Part of that is the ripple counting, and part of it is the unavoidable address decoding within the EEPROM. Half way between every address change, U4 latches clean stable mosfet gate drive data onto its eight outputs.
The eight higher order address bits select one of 256 different lookup tables.

U1 is an analog to digital converter capable of resolving twelve bits of which we only use nine, with an input voltage range of 0v to +4v. It requires a highly stable voltage reference of half the input measurement range, or +2.00 volts that comers from voltage regulator U12 which actually produces a 2.50v output.

DC input to be measured comes from the solar panels, or whatever is powering the inverter and appears on J1. Whatever input voltage range that actually is, is reduced to 0v to +4v by voltage divider R6, RV1, and R5. The purpose of RV1 is to allow for some component tolerances initially, but is also used to adjust the final output voltage of the inverter to exactly 220v.

The analog to digital measurement is initiated by U9C every second inverter cycle, in this case at 25Hz. The reason being that U1 has a maximum specified clocking rate and speed of 30 conversions per second. This one operates at 25Hz, but yours will be running at 30Hz which will be fine.

This type of dual slope analog to digital converter has the peculiarity that the twelve data output bits change after a delay period that is not constant, but varies with the measured voltage. Latch U8 reads the data from U1 to select the required lookup table, and that occurs exactly at the zero crossing point, so there is no waveform discontinuity as we jump between lookup tables.

The highest order bit from the analog to digital converter (B12) will be low over the first half of the dc input voltage range (0v to +2v) and high over the second half of the input voltage range (+2v to +4v). This is inverted by U9D so that below +2v input, the output enable of latch U8 will be tri stated into the high impedance state for input voltages lower than +2v.

So for dc input voltages below half full scale U8 output is high impedance, and pull down resistors RP1 cause the high order address bits to be 00, so we are always on the lowest lookup table below half the full scale input voltage. From half scale up to full scale voltage measurement, the analog to digital converter ranges from 00 to FF and we get to address our 256 different lookup tables. Above full scale input voltage, the analog to digital converter sticks at FF, but we should never get up that high.

So the result is, the inverter can voltage regulate over a 2:1 dc input voltage. Below the minimum input voltage the inverter still runs, but it will drop out of voltage regulation, as its stuck on the lowest lookup table. Above full maximum rated input voltage, it again drops out of voltage regulation stuck on the highest lookup table.

The data output bits look "funny" because they are not numbers but bit instructions as to what all the sixteen mosfet gates need to do to create (up to) 81 different voltage steps. There are 81 possible data states only, out of the possible 256, and it's really a lookup table within a lookup table, and it all looks like garbage.

But an over simplistic glance into this trick might help.

At the highest positive voltage step we want to switch on all four inverters in the positive direction so data might look like 1010 1010 (AA hex)

At the highest negative voltage step we wish to switch on all four inverters in the negative direction, so data might look like 0101 0101 (55 hex)

At the zero crossing it might be all inverters zero voltage 0000 0000 (00 hex)

It's actually a bit more complicated than that, but that is just to show the concept, and explain why all the data in the EEPROM looks like rubbish. We can go into all that a bit more deeply later.

Edited by LadyN 2019-03-13

Warpspeed
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Posted: 09:53pm 11 Mar 2019

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Natasha, thank you for starting a new thread.
The above schematic for the control board did not come out very well, so here it is again.

And here is the actual control board:

Just connect this up to the dc source, solar, battery, (or whatever) and it produces all the required mosfet gate drive waveforms for four inverters and provides voltage regulation without requiring any voltage feedback.

Edited by Warpspeed 2019-03-13

Cheers, �Tony.

hary
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Posted: 07:23pm 30 Apr 2019

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Warpspeed said and provides voltage regulation without requiring any voltage feedback.

I wonder how's that possible ?

LadyN

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Posted: 08:11pm 30 Apr 2019

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Tony meant line regulation and not load regulation of course.

For load regulation, voltage feedback will be necessary. No way around physics.

I of course don't know what I don't know.

Warpspeed
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Posted: 09:03pm 30 Apr 2019

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hary said

Warpspeed said and provides voltage regulation without requiring any voltage feedback.

I wonder how's that possible ?

Think of it like this Hary.

Suppose we designed an inverter that always feeds a constant ac voltage into the primary of a transformer.
As the incoming dc voltage varies up and down, the inverter compensates exactly for these incoming dc variations ahead of the transformer.

If the load on the inverter stays exactly the same, the output voltage will remain perfectly constant in amplitude over a very widely changing dc input voltage.

If the load changes, the output voltage will fall very slightly with increasing load, mainly due to resistive losses in the transformer windings and the mosfets. The drop in voltage is not serious, and can be ignored for a practical real world inverter.

The interesting thing about this, is that the input voltage correction can act very fast indeed, and be completed in one very swift correctional step.
If the shift in gain is carried out right at the zero crossing point, there will be no disturbance to waveform continuity, even for massive voltage corrections.

With voltage feedback, the inverter output voltage HAS TO ACTUALLY FALL before correction can even begin. Correction then has to be fairly gradual, to prevent any over correction, which will definitely lead to instability problems.

Its also a lot easier to measure a dc voltage quickly and accurately. An ac voltage is constantly varying over each cycle, so rectification and some averaging (smoothing) is required, all of which is SLOW and further adds to the feedback response time.

So the input voltage correction scheme is very fast, accurate, and requires fewer parts.
There will be some small residual output voltage error that changes with inverter loading, and there are ways to get around that.

The extra parts count and complexity are arguably just not worth the trouble.
The grid goes up and down in voltage all the time, and everything works just fine.

What is more objectionable is light flicker during sudden step load changes, and what is needed is very rapid speed of response to load changes, rather than always having a precisely exact output voltage.Edited by Warpspeed 2019-05-02

Cheers, �Tony.

hary
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Posted: 09:37pm 30 Apr 2019

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All this make actually lot of sense indeed !

Thanks for all the detailed explication !

That wouldn't have been my chosen route at first sight.

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