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Forum Index : Microcontroller and PC projects : Hardware bug in RP2350

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TassyJim

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Posted: 12:54am 30 Aug 2024
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  Grogster said  This all sounds like fun!

However, the takeaway/workaround for this would seem to be pretty simple:

1) DO NOT use the PULLDOWN option, and Peter will quite probably remove that from the code
2) Use 10k external pull-ups or pull-downs.

....unless I am missing something?


Code that uses internal pulldowns will not be portable.
It is very plausible that some of the BITBANG routines use pulldowns internally. They all will need checking.
High impedance sources are likely to need a buffer to get the required drive.

Jim
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matherp
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Posted: 07:32am 30 Aug 2024
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I've checked the Pico firmware source and the only place pulldowns are used is when the user explicitly requests them with SETPIN DIN or SETPIN INT(H/L/B)
Accordingly, I don't intent to make rp2350 specific changes to the firmware so it will be up to the user to avoid pulldowns when using relevant releases of the chip. Who knows they may fix it sometime.
 
TassyJim

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Posted: 07:41am 30 Aug 2024
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  matherp said  I've checked the Pico firmware source and the only place pulldowns are used is when the user explicitly requests them with SETPIN DIN or SETPIN INT(H/L/B)

That's good news.

I will keep testing my collection of sensors as time permits but so far, all is good!

Jim
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Mixtel90

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Posted: 07:49am 30 Aug 2024
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Since internal pullups and pulldowns on the majority of microprocessors and microcontrollers are generally poor and only ever used over short distances it's not really a big issue anyway. When used in commercial applications (which is where RPi want to sell most of these) there will be external resistors (unless the design is *really* bad).

The important thing is that pullups work. They are far more prevalent and used for very important stuff like on-board short range I2C and SPI.

It will confuse beginners but I'm afraid that the literature aimed at them will have to be suitable. Most seem to use pulldown for buttons and switches anyway.

Since this bug doesn't prevent the chip from being used in a commercial environment I doubt very much if they'll bother fixing it.
Mick

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PhenixRising
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Posted: 08:41am 30 Aug 2024
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Thanks for the summary, guys. Precisely what I was about to ask for and kudos to Volhout for bringing the issue to our attention  
 
Grogster

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Posted: 10:55pm 30 Aug 2024
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It must be something of a nightmare, designing a new die mask for chip production.
We all know how easy it is to have bugs in your CODE, and that extends to "Bugs" in the silicon also.  When designing a die, it needs to be 100% perfectly correct right from the off - a big ask, when you look at the complexity of a modern chip.

Sure, just like us PCB designers, you do prototype runs to make sure everything is OK, but just like with PCB prototypes, you find and fix all the problems you THINK you missed.....only to find AFTER the thing goes into production, there was something else subtle you missed!

Any PCB can easily have a new revision made to fix any layout error, but that is pretty much impossible with a silicon die after the prototype is released.

Revision 2 etc dies do exist for chips, but as Volhort mentioned earlier.....cost big bucks!
So the expense has to be worth it.
I don't envy die designers!  
Smoke makes things work. When the smoke gets out, it stops!
 
Volhout
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Posted: 01:04pm 31 Aug 2024
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Dies are going through several steps in production. Most of the steps( creating the P and N junctions) are processed on multiple wafers. Your die now basically is a huge box of P and N channel fets.
The last few steps add the metal interconnect layers, to connect the fets into logic gates, adders, flipflops, and  such...the final product.

These steps are done for A0 ( first proto of the die), A1, second proto.
So A0 and A1 have the same fets, only connected differen when bugs must be fixed.

The chips we have are A2. So ot is the 3rd revision.

Summary: not all masks are changed, typically only the metal layer masks.

Volhout

Ps, there are 100's of dies on a single wafer, maybe even 1000's. And a whole wafer is processed. Not independent dies.
Edited 2024-08-31 23:07 by Volhout
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robert.rozee
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Posted: 07:14pm 31 Aug 2024
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it looks like ADC inputs are also impacted in an 'odd' sort of way that MAY, UNDER SPECIFIC USAGE, see oscillations coming out of the pin:
https://forums.raspberrypi.com/viewtopic.php?t=375631&start=50#p2249127

"Connect a low resistance pot (I used 5K) between 3.3V and ground and connect the wiper of the pot to pin 27 via a 1M resistor
[...]
When we examine the anomalous signal on the scope (200MHz Siglent SDS1202-XE) we see oscillations with a peak amplitude near enough to Vdd and a pulse width of 10ms but with a random interval between pulses which is at least 50ms but which can go out to several hundred ms - this is why the DVM only shows a relatively low voltage
"

looks like the bottom line may well be that all inputs need to be driven with a somewhat low-impedance source, in the case of analog inputs a buffer opamp wired for unity gain would be a good choice.


cheers,
rob   :-)


addendum:
have added the words in red above: "
MAY, UNDER SPECIFIC USAGE". it seems that ajay_m in the above linked post may be resetting the pin status between reads, which in the RP2040 has proven unproblematic, but with the RP2350 causes the behavior he is seeing.

it occurs to me that, in the case of MMbasic, one solution may to, when a pin is configured for digital I/O, always configured for weak pull-up. this will ensure that unless a pin is explicitly pulled low by a suitable external signal, the pin will always return '1' and sit in a known state. Peter could add this as a permanent configuration to the firmware, ie hardwire the PULLUP parameter to SETPIN for all but analog/ADC configurations.


cheers,
rob   :-)

Edited 2024-09-01 22:08 by robert.rozee
 
JanVolk
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Joined: 28/01/2023
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Posted: 06:07pm 14 Sep 2024
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Last week the manual for Raspberry RP2350 Datasheet was updated for the hardware bug GPIO RP2350-E9 on pages 1341 to 1343.

Jan.
 
Volhout
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Posted: 06:33pm 14 Sep 2024
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All adc s have in their dataset a definition of input impedance.
This guy uses a 1 meg series resistor.
Not one ADC I know works flawless with this high impedance. If that impedance is required, put an opamp buffer between input and adc.

Volhout
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Mixtel90

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Posted: 06:52pm 14 Sep 2024
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Agreed. It was a bit silly. The Datasheet says:
  Quote  The ADC input is capacitive. When sampling, the ADC places about 1pF across the input. Packaging, PCB routing, and
other external factors introduce additional capacitance. The effective impedance, even when sampling at 500 kS/s, is
over 100 kΩ. DC measurements have no need to buffer.

"Over 100K" doesn't imply that the input impedance is anywhere close to 1M. It probably means that they tested it at 200K and it was fine.
Mick

Zilog Inside! nascom.info for Nascom & Gemini
Preliminary MMBasic docs & my PCB designs
 
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